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DATA SHEET
MOS INTEGRATED CIRCUIT
MC-458CA721ESA,458CA721PSA,458CA721XSA
8M-WORD BY 72-BIT SYNCHRONOUS DYNAMIC RAM MODULE (SO DIMM)
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Description Features
Part number MC-458CA721ESA-A80 MC-458CA721ESA-A10 MC-458CA721PSA-A80 MC-458CA721PSA-A10 MC-458CA721XSA-A80 MC-458CA721XSA-A10
The MC-458CA721ESA, MC-458CA721PSA and 458CA721XSA are 8,388,608 words by 72 bits synchronous These modules provide high density and large quantities of memory in a small space without utilizing the surface-
dynamic RAM module (Small Outline DIMM) on which 5 pieces of 128M SDRAM: PD45128163 are assembled.
mounting technology on the printed circuit board. Decoupling capacitors are mounted on power supply line for noise reduction.
* 8,388,608 words by 72 bits organization (ECC type) * Clock frequency and access time from CLK
/CAS latency CL = 3 CL = 2 Clock frequency (MAX.) 125 MHz 100 MHz Access time from CLK (MAX.) 6 ns 6 ns
* Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge * Pulsed interface * Possible to assert random column address in every cycle * Programmable burst-length (1, 2, 4, 8 and Full Page) * Programmable /CAS latency (2, 3) * Automatic precharge and controlled precharge * CBR (Auto) refresh and self refresh * Single 3.3 V 0.3 V power supply
* Quad internal banks controlled by BA0, BA1 (Bank Select) * Programmable wrap sequence (Sequential / Interleave)
Document No. E0067N10 (1st edition) (Previous No. M14494EJ3V0DS00) Date Published January 2001 CP (K) Printed in Japan
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The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all devices/types available in every country. Please check with local Elpida Memory, Inc. for availability and additional information.
This product became EOL in September, 2002.
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
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CL = 3 100 MHz 77 MHz 6 ns 7 ns 6 ns 6 ns CL = 2 CL = 3 125 MHz 100 MHz CL = 2 CL = 3 100 MHz 77 MHz 6 ns 7 ns 6 ns 6 ns CL = 2 CL = 3 CL = 2 125 MHz 100 MHz CL = 3 100 MHz 77 MHz 6 ns 7 ns CL = 2
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MC-458CA721ESA, 458CA721PSA, 458CA721XSA
* LVTTL compatible * 4,096 refresh cycles/64 ms * Burst termination by Burst Stop command and Precharge command * 144-pin small outline dual in-line memory module (Pin pitch = 0.8 mm) * Unbuffered type * Serial PD
Ordering Information
Part number Clock frequency MHz (MAX.) 125 MHz 100 MHz 125 MHz 100 MHz 125 MHz 100 MHz 144-pin Small Outline DIMM (Socket Type) Edge connector: Gold plated 31.75 mm height 5 piece of PD45128163G5 (Rev. E) (10.16mm (400) TSOP (II)) 5 piece of PD45128163G5 (Rev. P) (10.16mm (400) TSOP (II)) 5 piece of PD45128163G5 (Rev. X) (10.16mm (400) TSOP (II)) Package Mounted devices
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MC-458CA721ESA-A80 MC-458CA721ESA-A10 MC-458CA721PSA-A80 MC-458CA721PSA-A10 MC-458CA721XSA-A80 MC-458CA721XSA-A10
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Data Sheet E0067N10
MC-458CA721ESA, 458CA721PSA, 458CA721XSA
Pin Configuration
144-pin Dual In-line Memory Module Socket Type (Edge connector: Gold plated)
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60
Vss DQ 32 DQ 33 DQ 34 DQ 35 Vcc DQ 36 DQ 37 DQ 38 DQ 39 Vss DQMB4 DQMB5 Vcc A3 A4 A5 Vss DQ 40 DQ 41 DQ 42 DQ 43 Vcc DQ 44 DQ 45 DQ 46 DQ 47 Vss CB 4 CB 5
Vss DQ 0 DQ 1 DQ 2 DQ 3 VCC DQ 4 DQ 5 DQ 6 DQ 7 Vss DQMB0 DQMB1 VCC A0 A1 A2 Vss DQ 8 DQ 9 DQ 10 DQ 11 VCC DQ 12 DQ 13 DQ 14 DQ 15 Vss CB 0 CB 1
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59
/xxx indicates active low signal.
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62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144
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CLK0 CKE0 Vcc Vcc /RAS /CAS /WE NC /CS0 NC NC NC NC CLK1 Vss Vss CB 2 CB 6 CB 3 CB 7 VCC Vcc DQ 16 DQ 48 DQ 17 DQ 49 DQ 18 DQ 50 DQ 19 DQ 51 Vss Vss DQ 20 DQ 52 DQ 21 DQ 53 DQ 22 DQ 54 DQ 23 DQ 55 Vcc Vcc A6 A7 A8 BA0 (A13) Vss Vss A9 BA1 (A12) A10 A11 Vcc Vcc DQMB2 DQMB6 DQMB3 DQMB7 Vss Vss DQ 24 DQ 56 DQ 25 DQ 57 DQ 26 DQ 58 DQ 27 DQ 59 VCC Vcc DQ 28 DQ 60 DQ 29 DQ 61 DQ 30 DQ 62 DQ 31 DQ 63 Vss Vss SDA SCL VCC Vcc
61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143
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A0 - A11 [Row: A0 - A11, Column: A0 - A8] DQ0 - DQ63 CB0 - CB7 CKE0 /CS0 /RAS /CAS /WE CLK0, CLK1 : Clock Input DQMB0 - DQMB7 SDA SCL VCC VSS NC : Ground
Data Sheet E0067N10
: Address Inputs
BA0(A13), BA1(A12) : SDRAM Bank Select : Data Inputs/Outputs : Data Inputs/Outputs : Clock Enable Input
: Chip Select Input : Row Address Strobe
: Column Address Strobe : Write Enable : Serial Data I/O for PD : DQ Mask Enable : Clock Input for PD
: Power Supply
: No Connection
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MC-458CA721ESA, 458CA721PSA, 458CA721XSA
Block Diagram
/WE /CS0 DQMB0 DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 DQMB1 LDQM DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 UDQM DQ 8 DQ 9 DQ 10 DQ 11 DQ 12 DQ 13 DQ 14 DQ 15 D0
/CS /WE
DQMB4 DQ 32 DQ 33 DQ 34 DQ 35 DQ 36 DQ 37 DQ 38 DQ 39 DQMB5 DQ 40 DQ 41 DQ 42 DQ 43 DQ 44 DQ 45 DQ 46 DQ 47
LDQM DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 UDQM DQ 8 DQ 9 DQ 10 DQ 11 DQ 12 DQ 13 DQ 14 DQ 15
/CS
/WE
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DQ 8 DQ 9 DQ 10 DQ 11 DQ 12 DQ 13 DQ 14 DQ 15 CB 0 CB 1 CB 2 CB 3 CB 4 CB 5 CB 6 CB 7 DQMB2 DQ 16 DQ 17 DQ 18 DQ 19 DQ 20 DQ 21 DQ 22 DQ 23 DQMB3 DQ 24 DQ 25 DQ 26 DQ 27 DQ 28 DQ 29 DQ 30 DQ 31
D3
LDQM DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 UDQM DQ 8 DQ 9
/CS
/WE
DQMB6 DQ 48 DQ 49 DQ 50 DQ 51 DQ 52 DQ 53 DQ 54 DQ 55 DQMB7 DQ 56 DQ 57 DQ 58 DQ 59 DQ 60 DQ 61 DQ 62
LDQM DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 UDQM DQ 8 DQ 9
/CS
/WE
Remarks 1. D0 - D4: PD45128163 (2M words x 16 bits x 4 banks) 2. The value of all resistors is 10 .
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D1 DQ 10 DQ 11 DQ 12 DQ 13 DQ 14 DQ 15 LDQM DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7
/CS /WE
D4
UDQM DQ 8 DQ 9
DQ 10 DQ 11 DQ 12 DQ 13 DQ 14 DQ 15
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DQ 10 DQ 11 DQ 12 DQ 13 DQ 14 DQ 15 DQ 63 SERIAL PD VCC SCL SDA C A0 A1 A2 VSS D2 A0 - A11 A0 - A11 : D0 - D4 A13 : D0 - D4 A12 : D0 - D4 CLK0 BA0 BA1 10 CLK1 /RAS /RAS : D0 - D4 /CAS CKE0 /CAS : D0 - D4 CKE : D0 - D4
D0 - D4 D0 - D4
CLK : D0 - D4
10 pF
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Data Sheet E0067N10
MC-458CA721ESA, 458CA721PSA, 458CA721XSA
Electrical Specifications
* All voltages are referenced to VSS (GND). * After power up, wait more than 100 s and then, execute power on sequence and CBR (Auto) refresh before proper device operation is achieved.
Absolute Maximum Ratings
Parameter Voltage on power supply pin relative to GND Voltage on input pin relative to GND Short circuit output current Power dissipation Symbol VCC VT IO PD TA Tstg Condition Rating -0.5 to +4.6 -0.5 to +4.6 50 5 0 to 70 -55 to +125 Unit V V mA W C C
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Storage temperature
Operating ambient temperature
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter Supply voltage High level input voltage Low level input voltage Operating ambient temperature Symbol VCC VIH VIL TA Condition MIN. 3.0 TYP. 3.3 MAX. 3.6 Unit V V V C
Capacitance (TA = 25 C, f = 1 MHz)
Parameter Input capacitance
Data input/output capacitance
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2.0 -0.3 0 70 Symbol CI1 CI2 CI3 CI4 CI5 Test condition MIN. 17 TYP. A0 - A11, BA0(A13), BA1(A12), /RAS, /CAS, /WE CLK0 34 23 18 37 30 30 CKE0 /CS0 18 5 DQMB0 - DQMB7 CI/O DQ0 - DQ63, CB0 - CB7 5 13
Data Sheet E0067N10
VCC + 0.3 +0.8
MAX.
Unit pF
16.5 pF
ct
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MC-458CA721ESA, 458CA721PSA, 458CA721XSA
DC Characteristics (Recommended Operating Conditions unless otherwise noted)
Parameter Operating current Symbol ICC1 Test condition Burst length = 1, tRC tRC(MIN.) /CAS latency = 2 -A80 -A10 /CAS latency = 3 -A80 -A10 Precharge standby current in power down mode Precharge standby current in non power down mode ICC2P ICC2PS ICC2N CKE VIL(MAX.), tCK = 15 ns CKE VIL(MAX.), tCK = CKE VIH(MIN.), tCK = 15 ns, /CS VIH(MIN.), Input signals are changed one time during 30 ns. ICC2NS ICC3P ICC3PS ICC3N CKE VIH(MIN.), tCK = , Input signals are stable. CKE VIL(MAX.), tCK = 15 ns CKE VIL(MAX.), tCK = CKE VIH(MIN.), tCK = 15 ns, /CS VIH(MIN.), Input signals are changed one time during 30 ns. ICC3NS ICC4 CKE VIH(MIN.), tCK = , Input signals are stable. tCK tCK(MIN.), IO = 0 mA /CAS latency = 2 -A80 -A10 /CAS latency = 3 -A80 -A10 CBR (Auto) refresh current ICC5 tRC tRC(MIN.) /CAS latency = 2 -A80 100 725 550 875 700 1,150 mA 3 mA 2 40 25 20 150 mA mA 5 5 100 mA mA 550 MIN. MAX. 550 Unit Notes mA 1
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power down mode non power down mode Operating current (Burst mode) Self refresh current Input leakage current Output leakage current Low level output voltage
Active standby current in
Active standby current in
High level output voltage
Notes 1. ICC1 depends on output loading and cycle rates. Specified values are obtained with the output open. In addition to this, ICC1 is measured on condition that addresses are changed only one time during tCK(MIN.). 2. ICC4 depends on output loading and cycle rates. Specified values are obtained with the output open. In addition to this, ICC4 is measured on condition that addresses are changed only one time during tCK(MIN.). 3. ICC5 is measured on condition that addresses are changed only one time during tCK(MIN.).
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ICC6 II(L) IO(L) VOH VOL
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-A10 /CAS latency = 3 -A80 1,150 -A10 CKE 0.2 V 10 VI = 0 to 3.6 V, All other pins not under test = 0 V DOUT is disabled, VO = 0 to 3.6 V -5 +5 -1.5 2.4 +1.5 IO = - 4.0 mA IO = + 4.0 mA 0.4
Data Sheet E0067N10
mA
A A
V V
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MC-458CA721ESA, 458CA721PSA, 458CA721XSA
AC Characteristics (Recommended Operating Conditions unless otherwise noted)
Test Conditions
Parameter AC high level input voltage / low level input voltage Input timing measurement reference level Transition time (Input rise and fall time) Output timing measurement reference level Value 2.4 / 0.4 1.4 1 1.4 Unit V V ns V
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tCK tCH CLK 2.4 V 1.4 V 0.4 V tSETUP tHOLD 2.4 V 1.4 V 0.4 V tAC tOH tCL
Input
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Output
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Data Sheet E0067N10
7
MC-458CA721ESA, 458CA721PSA, 458CA721XSA
Synchronous Characteristics
Parameter Symbol MIN. Clock cycle time /CAS latency = 3 /CAS latency = 2 Access time from CLK /CAS latency = 3 /CAS latency = 2 CLK high level width CLK low level width Data-out hold time tCK3 tCK2 tAC3 tAC2 tCH tCL tOH tLZ /CAS latency = 3 /CAS latency = 2 tHZ3 tHZ2 tDS tDH tAS tAH tCKS tCKH tCKSP tCMS 3 3 3 0 3 3 2 1 2 1 2 1 2 2 6 6 8 10 -A80 MAX. (125 MHz) (100 MHz) 6 6 3 3 3 0 3 3 2 1 2 1 2 1 2 2 6 7 MIN. 10 13 -A10 MAX. (100 MHz) (77 MHz) 6 7 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1 1 1 Unit Note
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Data-in setup time Data-in hold time Address setup time Address hold time CKE setup time CKE hold time
Data-out low-impedance time Data-out high-impedance time
CKE setup time (Power down exit)
Command (/CS0, /RAS, /CAS, /WE, DQMB0 - DQMB7) setup time
Command (/CS0, /RAS, /CAS, /WE, DQMB0 - DQMB7) hold time
Note 1. Output load
Remark These specifications are applied to the monolithic device.
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Output
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tCMH 1 1 ns
Z = 50 50 pF
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Data Sheet E0067N10
MC-458CA721ESA, 458CA721PSA, 458CA721XSA
Asynchronous Characteristics
Parameter Symbol MIN. ACT to REF/ACT command period (Operation) REF to REF/ACT command period (Refresh) ACT to PRE command period PRE to ACT command period Delay time ACT to READ/WRITE command ACT(one) to ACT(another) command period Data-in to PRE command period Data-in to ACT(REF) command /CAS latency = 3 period (Auto precharge) /CAS latency = 2 tRC tRC1 tRAS tRP tRCD tRRD tDPL tDAL3 tDAL2 tRSC tT tREF 70 70 48 20 20 16 8 1CLK+20 1CLK+20 2 0.5 30 64 120,000 -A80 MAX. MIN. 70 70 50 20 20 20 10 1CLK+20 1CLK+20 2 1 30 64 120,000 -A10 MAX. ns ns ns ns ns ns ns ns ns CLK ns ms Unit Note
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Transition time
Mode register set cycle time
Refresh time (4,096 refresh cycles)
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Data Sheet E0067N10
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MC-458CA721ESA, 458CA721PSA, 458CA721XSA
Serial PD
Byte No. 0 1 2 3 4 5 6 7 8 9 Function Described Defines the number of bytes written into serial PD memory Total number of bytes of serial PD memory Fundamental memory type Number of rows Number of columns Number of banks Data width Hex 80H 08H 04H 0CH 09H 01H 48H 00H 01H -A80 -A10 -A80 -A10 80H A0H 60H 60H 02H 80H 10H 10H 01H 8FH 04H Bit 7 1 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 1 0 Bit 6 0 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 Bit 5 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 Bit 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 Bit 3 0 1 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 Bit 2 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 Bit 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 Bit 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 0 0 1 1 0
(1/2)
Notes 128 bytes 256 bytes SDRAM 12 rows 9 columns 1 bank 72 bits 0 LVTTL 8 ns 10 ns 6 ns 6 ns ECC Normal x16 x16 1 clock 1, 2, 4, 8, F 4 banks
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10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25-26 27 tRP(MIN.) 28 tRRD(MIN.) 29 tRCD(MIN.) 30 tRAS(MIN.) 31
Data width (continued) Voltage interface
CL = 3 Cycle time
CL = 3 Access time
DIMM configuration type Refresh rate/type
SDRAM width
Error checking SDRAM width Minimum clock delay
Burst length supported Number of banks on each SDRAM /CAS latency supported /CS latency supported
/WE latency supported
SDRAM module attributes
SDRAM device attributes : General CL = 2 Cycle time
CL = 2 Access time
Module bank density
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-A80 -A10 -A80 -A10 -A80 -A10 -A80 -A10 -A80 -A10 -A80 -A10
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06H 0 0 0 0 0 1 1 0 01H 0 0 0 0 0 0 0 1 01H 0 0 0 0 0 0 0 1 00H 0 0 0 0 0 0 0 0 0EH 0 0 0 0 1 1 1 0 A0H 1 0 1 0 0 0 0 0 D0H 60H 1 1 0 1 0 0 0 0 0 1 1 0 0 0 0 0 70H 0 1 1 1 0 0 0 0 00H 0 0 0 0 0 0 0 0 14H 0 0 0 1 0 1 0 0 14H 0 0 0 1 0 1 0 0 10H 0 0 0 1 0 0 0 0 14H 0 0 0 1 0 1 0 0 14H 0 0 0 1 0 1 0 0 14H 0 0 0 1 0 1 0 0 30H 32H 10H 0 0 0 0 0 0 1 1 0 1 1 1 0 0 0 0 0 0 0 0 1 0 0 0
Data Sheet E0067N10
2, 3 0 0
10 ns 13 ns 6 ns
7 ns
20 ns 20 ns
16 ns 20 ns
20 ns 20 ns
ct
48 ns 50 ns 64M bytes
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MC-458CA721ESA, 458CA721PSA, 458CA721XSA
(2/2)
Byte No. 32 Function Described Command and address signal setup time 33 Command and address signal hold time 34 Data signal input setup time -A80 -A10 -A80 -A10 -A80 -A10 35 Data signal input hold time -A80 -A10 Hex 20H 20H 10H 10H 20H 20H 10H 10H 00H -A80 -A10 -A80 -A10 12H 12H 01H 67H Bit 7 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 6 0 0 0 0 0 0 0 0 0 0 0 0 1 Bit 5 1 1 0 0 1 1 0 0 0 0 0 0 1 Bit 4 0 0 1 1 0 0 1 1 0 1 1 0 0 Bit 3 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 2 0 0 0 0 0 0 0 0 0 0 0 0 1 Bit 1 0 0 0 0 0 0 0 0 0 1 1 0 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1.2 A 1.2 A Notes 2 ns 2 ns 1 ns 1 ns 2 ns 2 ns 1 ns 1 ns
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36-61 62 SPD revision 63 Checksum 64-71 72 73-90 91-92 93-94 95-98 99-125 126 Mfg specific 127
for bytes 0 - 62
Manufacture's JEDEC ID code Manufacturing location Manufacture's P/N Revision code Manufacturing date
Assembly serial number
Intel specification frequency
Intel specification /CAS latency support
Timing Chart
Refer to the PD45128441, 45128841, 45128163 Data sheet (E0031N).
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-A80 64H 0 1 1 0 0 1 0 0 -A10 64H 0 1 1 0 0 1 0 0 -A80 87H 1 0 0 0 0 1 1 1 -A10 85H 1 0 0 0 0 1 0 1
Data Sheet E0067N10
100 MHz 100 MHz
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MC-458CA721ESA, 458CA721PSA, 458CA721XSA
Package Drawing
144-PIN DUAL IN-LINE MODULE (SOCKET TYPE)
A (AREA B) M1 (AREA B) R Y Z N
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M2 (AREA A) I F
Q M L
H C B
A
S
(OPTIONAL HOLES)
U1
U2 T
L
12
E D A1 (AREA A)
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ITEM A B A1 C D D1 D2 E F I L
MILLIMETERS 67.6 67.60.15 23.2 29.0 4.6 1.50.10 4.0 32.8 3.7 0.8 (T.P.)
detail of A part W
H
D2
3.3 20.0 31.750.15 9.75 22.0 3.8 MAX. R2.0 4.000.10 1.00.1 3.2 MIN.
M
M1 N
M2 Q R S
D1
X
V
1.8
T U1 U2
ct
4.0 MIN. V W X Z Y 0.25 MAX. 0.60.05 2.55 MIN. 2.0 MIN. 2.0 MIN. M144S-80A13
Data Sheet E0067N10
MC-458CA721ESA, 458CA721PSA, 458CA721XSA
[MEMO]
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Data Sheet E0067N10
13
MC-458CA721ESA, 458CA721PSA, 458CA721XSA
[MEMO]
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Data Sheet E0067N10
MC-458CA721ESA, 458CA721PSA, 458CA721XSA
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. HANDLING OF UNUSED INPUT PINS FOR CMOS
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2 Note: 3 Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. STATUS BEFORE INITIALIZATION OF MOS DEVICES
Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
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Data Sheet E0067N10
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MC-458CA721ESA, 458CA721PSA, 458CA721XSA
CAUTION FOR HANDLING MEMORY MODULES
When handling or inserting memory modules, be sure not to touch any components on the modules, such as the memory IC, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these components to prevent damaging them. When re-packing memory modules, be sure the modules are NOT touching each other. Modules in contact with other modules may cause excessive mechanical stress, which may damage the modules.
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* The information in this document is current as of September, 2000. The information is subject to change without notice. For actual design-in, refer to the latest publications of Elpida's data sheets or data books, etc., for the most up-to-date specifications of Elpida semiconductor products. Not all products and/or types are available in every country. Please check with an Elpida Memory, Inc. for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without prior written consent of Elpida. Elpida assumes no responsibility for any errors that may appear in this document. * Elpida does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of Elpida semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of Elpida or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. Elpida assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While Elpida endeavours to enhance the quality, reliability and safety of Elpida semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in Elpida semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. * Elpida semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of Elpida semiconductor products is "Standard" unless otherwise expressly specified in Elpida's data sheets or data books, etc. If customers wish to use Elpida semiconductor products in applications not intended by Elpida, they must contact an Elpida Memory, Inc. in advance to determine Elpida's willingness to support a given application. (Note) (1) "Elpida" as used in this statement means Elpida Memory, Inc. and also includes its majority-owned subsidiaries. (2) "Elpida semiconductor products" means any semiconductor product developed or manufactured by or for Elpida (as defined above).
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M8E 00. 4

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